Arli, A.Ç.Colak, A.Gazi, O.2025-11-062025-11-0620179781538613054https://doi.org/10.1109/ICRAE.2017.8291440https://hdl.handle.net/20.500.12416/15717Polar coding is the first kind of the capacity achieving codes which are defined for binary-input discrete memoryless channels initially. Parallel processing property of the FPGA allows to decode faster with a margin of complexity. Xilinx System Generator as a practical tool to construct decoding designs in shorter time is a fact. In this study, FPGA implementation of decoding polar codes through Xilinx System Generator is shown. © 2023 Elsevier B.V., All rights reserved.eninfo:eu-repo/semantics/closedAccessCoding TheoryFPGAParallel DecodingConference Object10.1109/ICRAE.2017.82914402-s2.0-85050384005