WoS İndeksli Yayınlar Koleksiyonu

Permanent URI for this collectionhttps://hdl.handle.net/20.500.12416/8653

Browse

Filters

20151

Settings

Publisher: search.filters.publisher.Institute of Electrical and Electronics Engineers Inc.Subject: search.filters.subject.Parallel Processing

Search Results

Now showing 1 - 1 of 1
  • Conference Object
    Citation - WoS: 2
    Citation - Scopus: 2
    A Two Stage Template Matching Algorithm and Its Implementation on Fpga
    (Institute of Electrical and Electronics Engineers Inc., 2015) Sever, R.; Töreyin, B.U.; Aktaş, H.
    In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs. © 2015 IEEE.