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The implementation of a successive cancellation polar decoder on xilinx system generator

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dc.contributor.authorArlı, A. Çağrı
dc.contributor.authorÇolak, Ayşe
dc.contributor.authorGazi, Orhan
dc.contributor.authorID206005tr_TR
dc.contributor.authorID102896tr_TR
dc.date.accessioned2020-03-20T07:43:20Z
dc.date.available2020-03-20T07:43:20Z
dc.date.issued2017
dc.departmentÇankaya Üniversitesi, Mühendislik Fakültesi, Elektronik ve Haberleşme Mühendisliği Bölümüen_US
dc.description.abstractPolar coding is the first kind of the capacity achieving codes which are defined for binary-input discrete memoryless channels initially. Parallel processing property of the FPGA allows to decode faster with a margin of complexity. Xilinx System Generator as a practical tool to construct decoding designs in shorter time is a fact. In this study, FPGA implementation of decoding polar codes through Xilinx System Generator is shown.en_US
dc.identifier.citationArlı, A.Çağrı; Çolak, Ayşe; Gazi, Orhan, "The implementation of a successive cancellation polar decoder on xilinx system generator", 2017 24th IEEE International Conference On Electronics, Cıicuits And Systems (ICECS), pp.372-376, (2017).en_US
dc.identifier.endpage376en_US
dc.identifier.isbn9781538619117
dc.identifier.startpage372en_US
dc.identifier.urihttp://hdl.handle.net/20.500.12416/2705
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.relation.ispartof2017 24th IEEE International Conference On Electronics, Cıicuits And Systems (ICECS)en_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectCoding Theoryen_US
dc.subjectFPGAen_US
dc.subjectParalel Decodingen_US
dc.titleThe implementation of a successive cancellation polar decoder on xilinx system generatortr_TR
dc.titleThe Implementation of a Successive Cancellation Polar Decoder on Xilinx System Generatoren_US
dc.typeConference Objecten_US
dspace.entity.typePublication

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