A Two Stage Template Matching Algorithm and Its Implementation on Fpga
| dc.contributor.author | Sever, R. | |
| dc.contributor.author | Töreyin, B.U. | |
| dc.contributor.author | Aktaş, H. | |
| dc.date.accessioned | 2020-04-19T23:53:12Z | |
| dc.date.accessioned | 2025-09-18T13:26:44Z | |
| dc.date.available | 2020-04-19T23:53:12Z | |
| dc.date.available | 2025-09-18T13:26:44Z | |
| dc.date.issued | 2015 | |
| dc.description | Toreyin, Behcet Ugur/0000-0003-4406-2783; Aktas, Hakan/0000-0002-0188-7075 | en_US |
| dc.description.abstract | In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs. © 2015 IEEE. | en_US |
| dc.identifier.citation | Toreyin, Behcet Ugur; Aktas, Hakan; Sever, Refik, "A Two Stage Template Matching Algorithm and Its Implementation on FPGA", 23nd Signal Processing and Communications Applications Conference (SIU), pp. 2214-2217, (2015). | en_US |
| dc.identifier.doi | 10.1109/SIU.2015.7130315 | |
| dc.identifier.isbn | 9781467373869 | |
| dc.identifier.issn | 2165-0608 | |
| dc.identifier.scopus | 2-s2.0-84939170749 | |
| dc.identifier.uri | https://doi.org/10.1109/SIU.2015.7130315 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12416/12711 | |
| dc.language.iso | tr | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
| dc.relation.ispartof | 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings -- 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 -- 16 May 2015 through 19 May 2015 -- Malatya -- 113052 | en_US |
| dc.relation.ispartofseries | Signal Processing and Communications Applications Conference | |
| dc.rights | info:eu-repo/semantics/closedAccess | en_US |
| dc.subject | Field-Programmable-Gate-Array (Fpga) | en_US |
| dc.subject | Memorry Adressing | en_US |
| dc.subject | Parallel Processing | en_US |
| dc.subject | Sum Of Absolute Differences | en_US |
| dc.subject | Template Matching | en_US |
| dc.subject | Unmanned Air Vehicle (Uav) | en_US |
| dc.title | A Two Stage Template Matching Algorithm and Its Implementation on Fpga | en_US |
| dc.title | A Two Stage Template Matching Algorithm and Its Implementation on FPGA | tr_TR |
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| gdc.author.id | Toreyin, Behcet Ugur/0000-0003-4406-2783 | |
| gdc.author.id | Aktas, Hakan/0000-0002-0188-7075 | |
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| gdc.author.wosid | Aktaş, Hakan/Aao-3543-2020 | |
| gdc.author.wosid | Toreyin, Behcet Ugur/A-6780-2012 | |
| gdc.author.wosid | Aktas, Hakan/I-7860-2017 | |
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| gdc.description.department | Çankaya University | en_US |
| gdc.description.departmenttemp | Aktaş H., Elektrik-Elektronik Mühendisliʇi Bölümü, Akdeniz Üniversitesi, Antalya, Turkey; Sever R., Elektrik-Elektronik Mühendisliʇi Bölümü, Akdeniz Üniversitesi, Antalya, Turkey; Töreyin B.U., Elektrik-Elektronik Mühendisliʇi Bölümü, Çankaya Üniversitesi, Ankara, Turkey | en_US |
| gdc.description.endpage | 2217 | en_US |
| gdc.description.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | en_US |
| gdc.description.startpage | 2214 | en_US |
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| gdc.virtual.author | Töreyin, Behçet Uğur | |
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