A Two Stage Template Matching Algorithm and Its Implementation on FPGA
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Date
2015
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IEEE
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Abstract
In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs.
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Keywords
Template Matching, Sum of Absolute Differences, Field-Programmable-Gate-Array (FPGA), Parallel Processing, Memory Adressing, Unmanned Air Vehicle (UAV)
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Citation
Toreyin, Behcet Ugur; Aktas, Hakan; Sever, Refik, "A Two Stage Template Matching Algorithm and Its Implementation on FPGA", 23nd Signal Processing and Communications Applications Conference (SIU), pp. 2214-2217, (2015).
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23nd Signal Processing and Communications Applications Conference (SIU)
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Start Page
2214
End Page
2217