A Two Stage Template Matching Algorithm and Its Implementation on FPGA
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Date
2015
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Institute of Electrical and Electronics Engineers Inc.
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Abstract
In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs. © 2015 IEEE.
Description
Toreyin, Behcet Ugur/0000-0003-4406-2783; Aktas, Hakan/0000-0002-0188-7075
Keywords
Field-Programmable-Gate-Array (Fpga), Memorry Adressing, Parallel Processing, Sum Of Absolute Differences, Template Matching, Unmanned Air Vehicle (Uav)
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Citation
Toreyin, Behcet Ugur; Aktas, Hakan; Sever, Refik, "A Two Stage Template Matching Algorithm and Its Implementation on FPGA", 23nd Signal Processing and Communications Applications Conference (SIU), pp. 2214-2217, (2015).
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Source
2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings -- 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 -- 16 May 2015 through 19 May 2015 -- Malatya -- 113052
Volume
Issue
Start Page
2214
End Page
2217