A Two Stage Template Matching Algorithm and Its Implementation on FPGA
| dc.contributor.author | Töreyin, Behçet Uğur | |
| dc.contributor.author | Sever, Refik | |
| dc.contributor.author | Töreyin, Behçet Uğur | |
| dc.contributor.authorID | 19325 | tr_TR |
| dc.date.accessioned | 2020-04-19T23:53:12Z | |
| dc.date.available | 2020-04-19T23:53:12Z | |
| dc.date.issued | 2015 | |
| dc.department | Çankaya Üniversitesi, Mühendislik Fakültesi, Elektrik Elektronik Mühendisliği Bölümü | en_US |
| dc.description.abstract | In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs. | en_US |
| dc.identifier.citation | Toreyin, Behcet Ugur; Aktas, Hakan; Sever, Refik, "A Two Stage Template Matching Algorithm and Its Implementation on FPGA", 23nd Signal Processing and Communications Applications Conference (SIU), pp. 2214-2217, (2015). | en_US |
| dc.identifier.endpage | 2217 | en_US |
| dc.identifier.issn | 2165-0608 | |
| dc.identifier.startpage | 2214 | en_US |
| dc.identifier.uri | https://hdl.handle.net/20.500.12416/3379 | |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.relation.ispartof | 23nd Signal Processing and Communications Applications Conference (SIU) | en_US |
| dc.rights | info:eu-repo/semantics/closedAccess | en_US |
| dc.subject | Template Matching | en_US |
| dc.subject | Sum of Absolute Differences | en_US |
| dc.subject | Field-Programmable-Gate-Array (FPGA) | en_US |
| dc.subject | Parallel Processing | en_US |
| dc.subject | Memory Adressing | en_US |
| dc.subject | Unmanned Air Vehicle (UAV) | en_US |
| dc.title | A Two Stage Template Matching Algorithm and Its Implementation on FPGA | tr_TR |
| dc.title | A Two Stage Template Matching Algorithm and Its Implementation on Fpga | en_US |
| dc.type | Conference Object | en_US |
| dspace.entity.type | Publication | |
| relation.isAuthorOfPublication | 31d067df-3d94-4058-a635-943b70f82ea4 | |
| relation.isAuthorOfPublication.latestForDiscovery | 31d067df-3d94-4058-a635-943b70f82ea4 |
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