The Implementation of a Successive Cancellation Polar Decoder on Xilinx System Generator
| dc.contributor.author | Colak, Ayse | |
| dc.contributor.author | Gazi, Orhan | |
| dc.contributor.author | Arli, A. Cagri | |
| dc.contributor.authorID | 206005 | tr_TR |
| dc.contributor.authorID | 102896 | tr_TR |
| dc.contributor.other | 06.02. Elektronik ve Haberleşme Mühendisliği | |
| dc.contributor.other | 06. Mühendislik Fakültesi | |
| dc.contributor.other | 01. Çankaya Üniversitesi | |
| dc.date.accessioned | 2020-03-20T07:43:20Z | |
| dc.date.accessioned | 2025-09-18T12:05:26Z | |
| dc.date.available | 2020-03-20T07:43:20Z | |
| dc.date.available | 2025-09-18T12:05:26Z | |
| dc.date.issued | 2017 | |
| dc.description.abstract | Polar coding is the first kind of the capacity achieving codes which are defined for binary-input discrete memoryless channels initially. Parallel processing property of the FPGA allows to decode faster with a margin of complexity. Xilinx System Generator as a practical tool to construct decoding designs in shorter time is a fact. In this study, FPGA implementation of decoding polar codes through Xilinx System Generator is shown. | en_US |
| dc.identifier.citation | Arlı, A.Çağrı; Çolak, Ayşe; Gazi, Orhan, "The implementation of a successive cancellation polar decoder on xilinx system generator", 2017 24th IEEE International Conference On Electronics, Cıicuits And Systems (ICECS), pp.372-376, (2017). | en_US |
| dc.identifier.doi | 10.1109/ICECS.2017.8291995 | |
| dc.identifier.isbn | 9781538619117 | |
| dc.identifier.scopus | 2-s2.0-85047358304 | |
| dc.identifier.uri | https://doi.org/10.1109/ICECS.2017.8291995 | |
| dc.identifier.uri | https://hdl.handle.net/123456789/10624 | |
| dc.language.iso | en | en_US |
| dc.publisher | Ieee | en_US |
| dc.relation.ispartof | 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS) -- DEC 05-08, 2017 -- Batumi, GEORGIA | en_US |
| dc.relation.ispartofseries | IEEE International Conference on Electronics Circuits and Systems | |
| dc.rights | info:eu-repo/semantics/closedAccess | en_US |
| dc.subject | Coding Theory | en_US |
| dc.subject | Fpga | en_US |
| dc.subject | Paralel Decoding | en_US |
| dc.title | The Implementation of a Successive Cancellation Polar Decoder on Xilinx System Generator | en_US |
| dc.title | The implementation of a successive cancellation polar decoder on xilinx system generator | tr_TR |
| dc.type | Conference Object | en_US |
| dspace.entity.type | Publication | |
| gdc.author.institutional | Gazi, Orhan | |
| gdc.author.scopusid | 57202151857 | |
| gdc.author.scopusid | 57225318436 | |
| gdc.author.scopusid | 14067353100 | |
| gdc.author.wosid | Arli, Ahmet/Aab-9644-2019 | |
| gdc.description.department | Çankaya University | en_US |
| gdc.description.departmenttemp | [Arli, A. Cagri; Colak, Ayse; Gazi, Orhan] Cankaya Univ, Elect & Commun Engn, Ankara, Turkey | en_US |
| gdc.description.endpage | 376 | en_US |
| gdc.description.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | en_US |
| gdc.description.startpage | 372 | en_US |
| gdc.description.volume | 2018-January | en_US |
| gdc.description.woscitationindex | Conference Proceedings Citation Index - Science | |
| gdc.identifier.openalex | W2787214824 | |
| gdc.identifier.wos | WOS:000426974200088 | |
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| gdc.openalex.normalizedpercentile | 0.25 | |
| gdc.opencitations.count | 1 | |
| gdc.plumx.mendeley | 6 | |
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